The present invention relates to a level shift circuit used for an interface between circuits with different power source voltages.
As processing is becoming finer in recent years, there has been a tendency toward reducing the power source voltage of circuits in semiconductor integrated circuits for the sake of device reliability. On the other hand, devices used in a system such as electronic equipment include a device operated on the conventional power source voltage. To interface between the devices and the semiconductor integrated circuit using different power source voltages, generally, a level shift circuit is provided in the semiconductor integrated circuit.
Recently, also in a semiconductor integrated circuit, an optimum power source voltage is supplied to each of circuit blocks in order to reduce power consumption. To interface among the circuit blocks of different power source voltages, a level shift circuit is also used. It is expected that importance of the level shift circuit is increasing in future.
A conventional level shift circuit is disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 6-209256. FIG. 29 shows an example of such a conventional level shift circuit. Shown in the diagram are N-type transistors 1 and 2, P-type transistors 3 and 4, a high voltage power source VDD, a ground power source VSS, an input signal IN, an inverted input signal XIN, an output signal OUT, and an inverted output signal XOUT. To the gate electrodes of the N-type transistors 1 and 2, the input signal IN and the inverted input signal XIN are input, respectively. The source electrodes of the N-type transistors 1 and 2 are connected to the ground power source VSS. The drain electrodes of the P-type transistors 3 and 4 are connected to the drain electrodes of the N-type transistors 1 and 2, and the source electrodes of the P-type transistors 3 and 4 are connected to the high voltage power source VDD. The P-type transistors 3 and 4 are cross-coupled in such a manner that the gate electrode of one of the P-type transistors 3 and 4 is connected to the drain electrode of the other transistor. The inverted output signal XOUT is output from the connection point between the P-type transistor 3 and the N-type transistor 1, and the output signal OUT is output from the connection point between the P-type transistor 4 and the N-type transistor 2.
The operation of the conventional level shift circuit will now be described. As an example, the operation will be described on assumption that the amplification level of the input signal IN and the inverted input signal XIN is 1.5V, the power source potential of the high voltage power source VDD is 3V, the potential of the ground power source VSS is 0V, and the amplitude level of the output signal OUT and the inverted output signal XOUT is 3V.
First, it is assumed that, as the initial state, the input signal IN is 0V, the inverted input signal XIN is 1.5V, the output signal OUT is 0V, and the inverted output signal XOUT is 3V. At this time, the N-type transistor 1 and the P-type transistor 4 are in a non-conducting state, and the N-type transistor 2 and the P-type transistor 3 are in a conducting state.
The case where the input signal IN changes to 1.5V and the inverted input signal XIN changes to 0V will now be considered. By the change, the N-type transistor 1 shifts to the conducting state, and the N-type transistor 2 shifts to the non-conducting state. Since the P-type transistor 3 is in the conducting state at this time, the potential of the inverted output signal XOUT decreases to an intermediate value determined by the ratio between conduction resistance values of the N-type transistor 1 and the P-type transistor 3. When the intermediate value exceeds the threshold voltage of the P-type transistor 4, the P-type transistor 4 shifts to the conducting state to increase the potential of the output signal OUT. When the potential of the output signal OUT rises, the P-type transistor 3 shifts to the non-conducting state, so that the conduction resistance value of the P-type transistor 3 rises and the potential of the inverted output signal XOUT further decreases.
Due to such positive feedback, the output signal OUT changes to 3V and the inverted output signal XOUT changes to 0V, thereby completing the operation of shifting the input signal of the low amplitude level to the output signal of the high amplitude level. Therefore, for example, a signal of a low power source voltage level in the semiconductor integrated circuit can be shifted to an outside signal of a high power source voltage level.
It was, however, found that when the power source voltage decreases more in the conventional level shift circuit, the following problems become conspicuous. Specifically, in the level shift circuit shown in FIG. 29, a transistor of a high withstand voltage and having a thick gate oxide film so as to withstand a high voltage is used as each of the N-type transistors 1 and 2. Generally, the transistor of a high withstand voltage has a large threshold voltage (for example, 0.5V). Consequently, when the voltage level (power source voltage level) of the input signal IN and the inverted input signal XIN drops close to the threshold voltage (for example, 0.7V) of the N-type transistors 1 and 2, the capability of the N-type transistors 1 and 2 for receiving the signal IN and XIN by their gate electrodes sharply deteriorates. As a result, when the signals IN and XIN change from 0V to the predetermined voltage level (0.7V), the operation of the N-type transistors 1 and 2 on the side of shifting to the conducting state is slow, and a problem occurs such that the operation speed of the level shift circuit as a whole deteriorates.
As described above, there is a tendency that the power source voltage in the semiconductor integrated circuit is becoming lower as microfabrication advances in recent years. Consequently, as the level of the voltage further decreases, it is becoming an important issue to shift a signal of the low voltage level to a signal of the high voltage level at speed as high as possible.